Method of fabricating CMOS using Si-B layer to form source/drain extension junction

ABSTRACT

A method of fabricating a CMOS transistor using Si—B layer to form a source/drain extension junction is disclosed. The fabrication includes the steps as follows; First, a p-type semiconductor substrate and an n-well region are provided. Afterwards, a shallow trench isolation (STI) is formed into the p-type semiconductor substrate and the n-well region, thereby forming a plurality of active regions therebetween. A channel is formed into the p-type semiconductor substrate and the n-well region. Then, a PMOSFET gate pattern and an NMOSFET gate pattern are formed over the p-type semiconductor substrate and the n-well region. A first defined photoresist layer is formed over the n-well region. Afterwards, the n − -type dopant is implanted into the p-type semiconductor substrate to form an n − -type lightly doped source/drain. Then the first defined photoresist layer is removed. A first dielectric layer is deposited over the p-type semiconductor substrate and the n-well region. A second defined photoresist layer is formed over the first dielectric layer. Afterwards, a portion of the first dielectric layer is firstly etched over the n-well region. Then an offset spacer is formed on the n-well region during a portion of the first dielectric layer etching step. Next, the second defined photoresist layer is removed. A Si—B (silicon-boron) layer is deposited over the n-well region and the first dielectric layer. The Si—B layer is oxidized to form a BSG layer, thereby firstly diffusing boron atoms into the n-well region to form a p − -type lightly doped source/drain. Afterwards, a second dielectric layer is deposited on the BSG layer. Next, a first BSG spacer and a second BSG spacer are formed, thereby etching a portion of the second dielectric layer, a portion of the BSG layer, and secondly etching a portion of the first dielectric layer. Afterwards, an n + -type heavily doped source/drain is formed into the p-type semiconductor substrate. Next, a p + -type heavily doped source/drain is formed into the n-well region. Finally, the first BSG spacer is annealed, thereby secondly diffusing boron atoms into the bottom region of the first BSG spacer to form a source/drain extension junction in a PMOSFET.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating complementarymetal-oxide-semiconductor (CMOS) transistor, and more particularly to amethod of fabricating CMOS transistor using Si—B layer to form asource/drain extension junction.

2. Description of the Prior Art

Recently, ultra large-scale integration (ULSI) semiconductortechnologies have dramatically increased the integrated circuit densityon the chips formed on the semiconductor substrate. This increase incircuit density has resulted from downsizing of the individual devicesand the resulting increase in device packing density. The reduction indevice size was achieved predominantly by recent advances inhigh-resolution photolithography, directional (anisotropic) plasmaetching, and other semiconductor technology innovations. However, futurerequirements for even greater circuit density are putting additionaldemand on the semiconductor processing technologies and on deviceelectrical requirements.

The fabrication of a metal-oxide-semiconductor field effect transistor(MOSFET) device is well-known. Generally, MOSFETs are manufactured byplacing an undoped polysilicon material over a relatively thin gateoxide. The polysilicon material and gate oxide is then patterned to forma gate conductor with source/drain regions adjacent to and on oppositesides of the gate conductor. The gate conductor and source/drain regionsare then implanted with an impurity dopant material. If the impuritydopant material used for forming the source/drain regions is n-type,then the resulting MOSFET is an NMOSFET (“n-channel”) transistor device.Conversely, if the source/drain dopant material is p-type, then theresulting MOSFET is a PMOSFET (“p-channel”) transistor device.

The gate conductor and adjacent source/drain regions are formed usingwell-known photolithography techniques. Gate conductors and source/drainregions arise in openings formed through a thick layer of what iscommonly referred to as field oxide (FOX). Those openings and thetransistors formed therein are termed active regions. The active regionsare therefore regions between field oxide regions. Metal interconnect isrouted over the field oxide to couple with the polysilicon gateconductor as well as with source/drain regions to complete the formationof an overall circuit structure.

Integrated circuits utilize either n-channel devices exclusively,p-channel devices exclusively, or a combination of both on unitarymonolithic substrate. While both types of devices can be formed, thedevices are distinguishable based on the source/drain impurity dopant.The method by which n-type dopant is used to form an n-channel deviceand p-type dopant is used to form a p-channel device entail uniqueproblems associated with each device. As layer densities increase, theproblems are exacerbated. Device failure can occur unless adjustmentsare made to processing parameters and processing steps. The n-channelprocessing must, in most instances, be dissimilar from p-channelprocessing due to the unique problems of each type of device. Theproblems inherent in n-channel fabrication will be discussed firstfollowed by p-channel.

The n-channel devices are particularly sensitive to so-called shortchannel effects. The distance between source and drain regions is oftenreferred to as the physical channel length. However, after implantationand subsequent diffusion of the source and drain, distance between thesource and drain regions becomes less than the physical channel lengthand is often referred to as the effective channel length. In VLSIdesigns, as the physical channel becomes small, the short channel effectbecomes a predominant problem.

Generally, the short channel effect impacts device operation by reducingdevice threshold voltages and increasing sub-threshold currents. As theeffective channel length becomes quite small, the depletion regionsassociated with the source and drain areas may extend toward one anotherand substantially occupy the channel area. Hence, some of the channelwill be partially depleted without any influence of gate voltage. As aresult, less gate charge is required to invert the channel of atransistor having a short effective channel length. Somewhat related tothreshold voltage lowering is the concept of sub-threshold current flow.Even at times when the gate voltage is below the threshold amount,current between the source and drain nonetheless exist for transistorshaving a relatively short effective channel length.

However, two of the primary causes of increased sub-threshold currentare punch-through and drain-induced barrier lowering. Punch-throughresults from the widening of the drain depletion region when areverse-bias voltage is applied across the drain-well diode. Theelectric field of the drain may eventually penetrate to the source area,thereby reducing the potential energy barrier of the source-to-bodyjunction. Punch-through current is therefore associated within thesubstrate bulk material, well below the substrate surface. Contrary topunch-through current, drain-induced barrier lowering for inducedcurrent occurs mostly at the substrate surface. Application of a drainvoltage can cause the surface potential to be lowered, resulting in alowered potential energy barrier at the surface and causing thesub-threshold current in the channel near the silicon-silicon dioxideinterface to be increased. One method in which to control short channeleffect is to increase the dopant concentration within the body of thedevice. Unfortunately, increasing dopant within the body deleteriouslyincreases potential gradients in the ensuing device.

Increasing the potential gradients produces an additional effect knownas hot carrier effect. The hot carrier effect is a phenomena by whichthe kinetic energy of the carriers (holes or electrons) is increased asthey are accelerated through large potential gradients and subsequentlybecome trapped within the gate oxide. The greatest potential gradient,often referred to as the maximum electric field, occurs near the drainduring saturated operation. More specifically, the electric field ispredominant at the lateral junction of the drain adjacent the channel.

Using the n-channel example, the electric field at the drain causeschannel electrons to gain kinetic energy. Electron-electron scatteringrandomizes the kinetic energy and the electrons become “hot”. Some ofthese hot electrons have enough energy to create electron-hole pairsthrough impact ionization of the silicon atoms. Electrons generated byimpact ionization join the flow of channel electrons, while the holeflows into the bulk to produce a substrate current in the device. Thesubstrate current is the first indication of the creation of hotcarriers in a device. For p-channel devices, the fundamentals of theprocess are essentially the same except that the role of holes andelectrons are reversed.

The hot carrier effect occurs when some of the hot carriers are injectedinto the gate oxide near the drain junction, where they induce damageand become trapped. Traps within the gate oxide generally becomeelectron traps, even if they are initially filled with holes. As aresult, there is a negative charge density in the gate oxide. Thetrapped charge accumulates with time, resulting in positive thresholdshifts in both n-channel and p-channel devices. It is known that sincehot electrons are more mobile than hot holes, the hot carrier effectcauses a greater threshold skew in n-channel devices than p-channeldevices. Nonetheless, a p-channel device will undergo negative thresholdskew.

Unless modifications are made to the transistor structure, the problemsof sub-threshold current and threshold shift resulting from shortchannel effect and hot carrier effect will remain. To overcome theseproblems, alternative drain structures such as double diffused drains(DDDs) and lightly doped drains (LDDs) must be used. The purpose of bothtypes of structures is the same: to absorb some of the potential intothe drain and thus reduce the maximum electric field. The popularity ofdouble diffused drain structures has given way to lightly doped drainstructures since double diffused drains cause unacceptably deepjunctions and deleterious junction capacitance.

A conventional lightly doped drain structure is one whereby a lightconcentration of dopant is self-aligned to the gate electrode followedby a heavier dopant self-aligned to the gate electrode on which twosidewall spacers have been formed. The purpose of the first implant doseis to produce a lightly doped section of both the source and drain areasat the gate edge near the channel. The second implant dose is spacedfrom the channel a distance dictated by the thickness of the sidewallspacer. Resulting from the first and second implants, a dopant gradientoccurs at the junction between the source and channel as well as thejunction between the drain and channel.

A properly defined lightly doped drain structure must be one whichminimizes hot carrier effect but not at the expense of excessivesource/drain resistance. The addition of a lightly doped drain implantadjacent the channel unfortunately adds resistance to the source/drainpath. This added resistance, generally known as parasitic resistance,can have many deleterious effects. First, parasitic resistance candecrease the saturation current (i.e., current above threshold). Second,parasitic resistance can decrease the overall speed of the transistor.

A properly designed lightly doped source/drain, which overcomes theabove problems, must therefore be applicable to both an n-channeltransistor and a p-channel transistor. However, the approach will beused in CMOS processes. The CMOS transistor is readily fabricated withinexisting process technologies. In accordance with many modem fabricationtechniques, it would be desirable that the improved CMOS transistor beformed having low resistance and the ultra shallow junction.

SUMMARY OF THE INVENTION

In accordance with the present invention, a method is provided forforming a complementary metal-oxide-semiconductor (CMOS) transistor oflow resistance and ultra shallow junction. However, the CMOS structureis typically formed including p-well CMOS transistor, n-well CMOStransistor, and twin-well CMOS transistor. Moreover, while the n-wellCMOS processes will be described in this embodiment other types of CMOSstructures can also be included. In this embodiment, the fabricationprocess includes the steps as follows. At first, a CMOS transistorregion is provided on and in a single crystal silicon substrate dopedwith a p-type dopant. Then an n-well region is formed into a p-typesemiconductor substrate. Afterwards, relatively deep shallow trenchisolation (STI) is formed into the p-type semiconductor substrate and aportion of the n-well region, thereby forming a PMOSFET active regionand an NMOSFET active region. A channel is formed into the PMOSFETactive region and the NMOSFET active region. Afterwards, a gate oxidelayer is formed on the PMOSFET active region and the NMOSFET activeregion. Then a polysilicon gate is deposited on the gate oxide layer.Next, the polysilicon gate and the gate oxide layer are etched to form aPMOSFET gate pattern on the PMOSFET active region and an NMOSFET gatepattern on the NMOSFEIT active region. A first defined photoresist layeris formed over the PMOSFET active region and a portion of the shallowtrench isolation. Afterwards, an n⁻-type dopant is implanted into theNMOSFET active region to form an n⁻-type lightly doped source/drain.Then the first defined photoresist layer is removed. A first dielectriclayer is deposited on the shallow trench isolation, the NMOSFET gatepattern, the PMOSFET gate pattern, the NMOSFET active region, and thePMOSFET active region. A second defined photoresist layer is formed overthe first dielectric layer. Afterwards, a portion of the firstdielectric layer is firstly etched on the PMOSFET active region and aportion of the shallow trench isolation. Then an offset spacer is formedon the PMOSFET active region during a portion of the first dielectriclayer-etching step. Next, the second defined photoresist layer isremoved. A Si—B (silicon-boron) layer is deposited on a portion of theshallow trench isolation, the PMOSFET active region, the PMOSFET gatepattern, the offset spacer, and the first dielectric layer. The Si—Blayer is oxidized to form a BSG layer, thereby firstly diffusing boronatoms into the PMOSFET active region to form a p⁻-type lightly dopedsource/drain. Afterwards, a second dielectric layer is deposited on theBSG layer. Next, a first BSG spacer and a second BSG spacer is formed,thereby etching a portion of the second dielectric layer, a portion ofthe BSG layer, and secondly etching a portion of the first dielectriclayer. Afterwards, a p⁺-type dopant is implanted into the PMOSFET activeregion to form a p⁺-type heavily doped source/drain. Next, an n⁺-typedopant is implanted into the NMOSFET active region to form an n⁺-typeheavily doped source/drain. Finally, the first BSG spacer is annealed,thereby secondly diffusing boron atoms into the bottom region of thefirst BSG spacer to form a source/drain extension junction in a PMOSFET.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of thisinvention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

FIGS. 1 through 9 show the cross-sectional views illustrative of variousstages in the CMOS transistor in accordance with one embodiment of thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A method of fabricating a complementary metal-oxide-semiconductor (CMOS)transistor using BSG film to form PMOS source/drain extension junctionwill now be described in detail. The CMOS structure is typically formed,including a p-well CMOS transistor, an n-well CMOS transistor, and atwin-well CMOS transistor. However, while the n-well CMOS processes willbe described in this embodiment, other types of CMOS structures can alsobe included. FIGS. 1 through 8 show the cross-sectional viewsillustrative of various stages in the CMOS transistor in accordance withone embodiment of the present invention.

Referring to FIG. 1, a CMOS transistor region is provided on and in alightly doped p-type single crystal silicon substrate, having a <100>crystallographic orientation. The p-type semiconductor substrate 10comprises a concentration less than about 1.0 E 15 atoms/cm³. Then then-well region 15 is formed, using ion implantation procedures andphosphorus (P) as an ion source, at an energy between about 100 KeV to200 KeV, to implant a dosage between about 1.0 E 12 to 1.0 E 13atoms/cm², then using a driving-in process, at a temperature about 1000°C. to form a concentration about 1.0 E 16 atoms/cm³, into the p-typesemiconductor substrate 10. Afterwards, a relatively deep shallow trenchisolation (STI) 20 is formed surrounding and electrically isolating theindividual device regions in which the p-type semiconductor substrate 10and a portion of the n-well region 15 are built, thereby forming aPMOSFET active region 500 and an NMOSFET active region 505. A channel 25is formed using ion implantation procedures and an ion source such asboron (B) or boron fluoride (BF₂), at an energy about 10 KeV, to implanta dosage about 1.0 E 12 atoms/cm², into the PMOSFET active region 500and the NMOSFET active region 505. Afterwards, a gate oxide layer 30 isformed, using thermal oxidation comprising a dry oxidation and a wetoxidation, on the PMOSFET active region 500 and the NMOSFET activeregion 505. The polysilicon layer is formed using low-pressure chemicalvapor deposition (LPCVD) procedures and silane (SiH₄) as a source gas,at a temperature between about 600° C. to 650° C. to a thickness betweenabout 1000 to 2500 angstroms. Next, the polysilicon gate 35 and the gateoxide layer 30 are etched to form a PMOSFET gate pattern 45 on thePMOSFET active region 500 and an NMOSFET gate pattern 40 on the NMOSFETactive region 505.

Referring to FIG. 2, a first defined photoresist layer 50A is formed onthe PMOSFET active region 500 and a portion of the shallow trenchisolation 20. Afterwards, an n⁻-type lightly doped source/drain 50 isformed, using ion implantation procedures and an ion source, such asphosphorus (P) or arsenic (As), at an energy less than about 30 KeV, toimplant a dosage between about 1.0 E 14 to 5.0 E 15 atoms/cm² into theNMOSFET active region 505. Then the first defined photoresist layer 50Ais removed.

Referring to FIG. 3, a first dielectric layer 60 is deposited,comprising silicon oxide, silicon nitride, or silicon oxide/siliconnitride, on the shallow trench isolation 20, the NMOSFET gate pattern40, the PMOSFET gate pattern 45, the NMOSFET active region 505, and thePMOSFET active region 500. The silicon oxide is deposited usinglow-pressure chemical vapor deposition (LPCVD) procedures and TEOS as asource gas, at a temperature between about 500° C. to 800° C. to athickness between about 50 to 300 angstroms. The silicon nitride isdeposited, using low pressure chemical vapor deposition (LPCVD)procedures, at a temperature about 750° C., to a thickness between about50 to 300 angstroms. The silicon oxide/silicon nitride is deposited,using low-pressure chemical vapor deposition (LPCVD) procedures, at atemperature between about 500° C. to 800° C. and to a thickness betweenabout 100 to 300 angstroms.

Referring to FIG. 4, a second defined photoresist layer 60A is formed onthe first dielectric layer 60. Afterwards, a portion of the firstdielectric layer 60 is firstly etched, using reactive ion etching (RIE)procedures with CHF.₃ as an etchant, on the PMOSFET active region 500and a portion of the shallow trench isolation 20. Then an offset spacer65 is formed on the PMOSFET active region 500 during a portion of thefirst dielectric layer 60 etching step. Next, the second definedphotoresist layer 60A is removed.

Referring to FIG. 5, a Si—B (silicon-boron) layer 70 is deposited, usingultra-high vacuum chemical vapor deposition (UHV/CVD) procedures and asource gas, such as SiH₄ and B₂H₆, a thickness between about 100 to 300angstroms, on a portion of the shallow trench isolation 20, the PMOSFECTactive region 500, the PMOSFET gate pattern 45, the offset spacer 65,and the first dielectric layer 60.

Referring to FIG. 6, the Si—B layer 70 (as shown in FIG. 5) is oxidized,using a rapid thermal processing (RTP), at a temperature between about800° C. to 1000° C., at a time between about 10 to 60 seconds, to formthe BSG layer 80, thereby firstly diffusing boron atoms into the PMOSFETactive region 500 to form a p⁻-type lightly doped source/drain 85. Theboron atoms have a concentration about 5.0 E 21 atoms/cm³. Afterwards, asecond dielectric layer 90 is deposited, comprising silicon oxide orsilicon nitride, on the BSG layer 80. The silicon oxide is deposited,using low pressure chemical vapor deposition (LPCVD) procedures and TEOSas a source gas, at a temperature between about 500° C. to 800° C., to athickness between about 500 to 2000 angstroms. The silicon nitride isdeposited, using low pressure chemical vapor deposition (LPCVD)procedures, at a temperature about 750° C., to a thickness between about500 to 2000 angstroms.

Referring to FIG. 7, a first BSG spacer 95 and a second BSG spacer 100is formed, thereby etching a portion of the second dielectric layer 90,a portion of the BSG layer 80, and secondly etching a portion of thefirst dielectric layer 60. The second dielectric layer 90, the BSG layer80, and the first dielectric layer 60 are etched, using reactive ionetching (RIE) procedures with CHF₃ as an etchant.

Referring to FIG. 8, a p⁺-type heavily doped source/drain 105 is formed,using ion implantation procedures and an ion source, such as boron (B)or boron fluoride (BF₂), at an energy between about 1 KeV to 80 KeV, toimplant a dosage between about 1.0 E 15 to 1.0 E 16 atoms/cm², into thePMOSFET active region 500. Afterwards, an n⁺-type heavily dopedsource/drain 110 is formed, using ion implantation procedures and an ionsource, such as phosphorus (P) or arsenic (As), at an energy betweenabout 10 KeV to 80 KeV, to implant a dosage between about 1.0 E 15 to1.0 E 16 atoms/cm², into the NMOSFET active region 505.

Referring to FIG. 9, the first BSG spacer 95 is annealed, using a rapidthermal processing (RTP), at a temperature between about 950° to 1050°C., at a time between about 10 to 60 seconds, thereby secondly diffusingboron atoms into the bottom region of the first BSG spacer 95 to form asource/drain extension junction 120 in a PMOSFET.

Although specific embodiments have been illustrated and described, itwill be obvious to those skilled in the art that various modificationsmay be made without departing from the spirit which is intended to belimited solely by the appended claims.

What is claimed is:
 1. A method of fabricating complementarymetal-oxide-semiconductor, said method comprising: providing asemiconductor substrate having a first conductivity type; forming a wellregion into said semiconductor substrate, said well region having asecond conductivity type, said second conductivity type being oppositeto said first conductivity type; forming a shallow trench isolation(STI) into said semiconductor substrate and said well region, therebyforming a plurality of active regions therebetween; forming a channelinto said semiconductor substrate and said well region; forming aPMOSFET gate pattern and a NMOSFET gate pattern over said semiconductorsubstrate and said well region; forming a first defined photoresistlayer over said well region; implanting a first dopant of said secondconductivity type into said semiconductor substrate to form a firstlightly doped source/drain; removing said first defined photoresistlayer; depositing a first insulating layer over said semiconductorsubstrate and said well region; forming a second defined photoresistlayer over said first insulating layer; firstly etching a portion ofsaid first insulating layer over said well region; forming an offsetspacer over said well region during a portion of said first insulatinglayer etching step; removing said second defined photoresist layer;depositing a Si—B (silicon-boron) layer over said well region and saidfirst insulating layer; oxidizing said Si—B layer to form a BSG layer,thereby firstly diffusing boron atoms into said well region to form asecond lightly doped source/drain; depositing a second insulating layeron said BSG layer; etching a portion of said second insulating layer, aportion of said BSG layer, and secondly etching a portion of said firstinsulating layer to form a first BSG spacer and a second BSG spacer;implanting a first dopant of said first conductivity type into said wellregion to form a first heavily doped source/drain; implanting a seconddopant of said second conductivity type into said semiconductorsubstrate to form a second heavily doped source/drain, where aconcentration of said second dopant is greater than that of said firstdopant; and annealing said first BSG spacer, thereby secondly diffusingsaid boron atoms thereof into a below region of said first BSG spacer toform a source/drain extension junction.
 2. The method according to claim1, wherein said semiconductor substrate comprises a concentration lessthan about 1.0 E 15 atoms/cm.sup.3.
 3. The method according to claim 1,wherein said first conductivity type comprises a p-type.
 4. The methodaccording to claim 1, wherein said well region is formed, comprising ionimplantation procedures and phosphorus (P) as an ion source, at a energybetween about 100 KeV to 200 KeV, to implant a dosage between about 1.0E 12 to 1.0 E 13 atoms/cm.sup.2, then using a driving-in process, at atemperature about 1000.degree.C., to form a concentration about 1.0 E 16atoms/cm.sup.3.
 5. The method according to claim 1, wherein said secondconductivity type comprises a n-type.
 6. The method according to claim1, wherein said active region comprises a PMOSFET active region.
 7. Themethod according to claim 1, wherein said active region comprises aNMOSFET active region.
 8. The method according to claim 1, wherein saidchannel is formed, comprising ion implantation procedures and boron (B)as an ion source, at a energy about 10 KeV, to implant a dosage about1.0 E 12 atoms/cm.sup.2.
 9. The method according to claim 1, whereinsaid channel is formed, comprising ion implantation procedures and boronfluoride (BF₂) as an ion source, at a energy about 10 KeV, to implant adosage about 1.0 E 12 atoms/cm.sup.2.
 10. The method according to claim1, wherein said PMOSFET gate pattern and said NMOSFET gate pattern areformed, comprising a polysilicon gate and a gate oxide layer.
 11. Themethod according to claim 10, wherein said polysilicon gate comprises apolysilicon layer and a tungsten silicon (WSi₂) layer.
 12. The methodaccording to claim 1, wherein said first lightly doped source/drain isformed, comprising ion implantation procedures and phosphorus (P) as anion source, at a energy less than about 30 KeV, to implant a dosagebetween about 1.0 E 14 to 5.0 E 15 atoms/ cm.sup.2.
 13. The methodaccording to claim 1, wherein said first lightly doped source/drain isformed, comprising ion implantation procedures and arsenic (As) as anion source, at a energy less than about 30 KeV, to implant a dosagebetween about 1.0 E 14 to 5.0 E 15 atoms/cm.sup.2.
 14. The methodaccording to claim 1, wherein said first insulating layer comprisessilicon oxide, using low pressure chemical vapor deposition (LPCVD)procedures and TEOS as a source gas, at a temperature between about500.degree. to 800.degree.C., to a thickness between about 50 to 300angstroms.
 15. The method according to claim 1, wherein said firstinsulating layer comprises silicon nitride, using low pressure chemicalvapor deposition (LPCVD) procedures, at a temperature about750.degree.C., to a thickness between about 50 to 300 angstroms.
 16. Themethod according to claim 1, wherein said first insulating layercomprises silicon oxide/silicon nitride, using low pressure chemicalvapor deposition (LPCVD) procedures, at a temperature between about500.degree. to 800.degree.C., to a thickness between about 100 to 300angstroms.
 17. The method according to claim 1, wherein said firstinsulating layer is firstly etched, comprising reactive ion etching(RIE) procedures with CHF.sub.3 as an etchant.
 18. The method accordingto claim 1, wherein said Si—B (silicon-boron) layer is deposited,comprising ultra-high vacuum chemical vapor deposition (UHV/CVD)procedures and a source gas, such as SiH₄ and B₂H₆, a thickness betweenabout 100 to 300 angstroms.
 19. The method according to claim 1, whereinsaid Si—B layer is oxidized to form said BSG layer, comprising a rapidthermal processing (RTP), at a temperature between about 800.degree. to1000.degree.C., at a time between about 10 to 60 seconds.
 20. The methodaccording to claim 1, wherein said boron atoms comprises a concentrationabout 5.0 E 21 atoms/cm.sup.3.
 21. The method according to claim 1,wherein said second insulating layer comprises silicon oxide, using lowpressure chemical vapor deposition (LPCVD) procedures and TEOS as asource gas, at a temperature between about 500.degree. to 800.degree.C.,to a thickness between about 500 to 2000 angstroms.
 22. The methodaccording to claim 1, wherein said second insulating layer comprisessilicon nitride, using low pressure chemical vapor deposition (LPCVD)procedures, at a temperature about 750.degree.C., to a thickness betweenabout 500 to 2000 angstroms.
 23. The method according to claim 1,wherein said second insulating layer is etched, comprising reactive ionetching (RIE) procedures with CHF.sub.3 as an etchant.
 24. The methodaccording to claim 1, wherein said BSG layer is etched, comprisingreactive ion etching (RIE) procedures with CHF.sub.3 as an etchant. 25.The method according to claim 1, wherein said first insulating layer issecondly etched, comprising reactive ion etching (RIE) procedures withCHF.sub.3 as an etchant.
 26. The method according to claim 1, whereinsaid first heavily doped source/drain is formed, comprising ionimplantation procedures and boron (B) as an ion source, at a energybetween about 1 KeV to 80 KeV, to implant a dosage between about 1.0 E15 to 1.0 E 16 atoms/cm.sup.2.
 27. The method according to claim 1,wherein said first heavily doped source/drain is formed, comprising ionimplantation procedures and boron fluoride (BF₂) as an ion source, at aenergy between about 1 KeV to 80 KeV, to implant a dosage between about1.0 E 15 to 1.0 E 16 atoms/cm.sup.2.
 28. The method according to claim1, wherein said second heavily doped source/drain is formed, comprisingion implantation procedures and phosphorus (P) as an ion source, at aenergy between about 10 KeV to 80 KeV, to implant a dosage between about1.0 E 15 to 1.0 E 16 atoms/cm.sup.2.
 29. The method according to claim1, wherein said second heavily doped source/drain is formed, comprisingion implantation a procedures and arsenic (As) as an ion source, at aenergy between about 10 KeV to 80 KeV, to implant a dosage between about1.0 E 15 to 1.0 E 16 atoms/cm.sup.2.
 30. The method according to claim1, wherein said boron atoms are secondly diffused, comprising a rapidthermal processing (RTP), at a temperature between about 950.degree. to1050.degree.C., at a time between about 10 to 60 seconds.
 31. A methodof fabricating complementary metal-oxide-semiconductor (CMOS), saidmethod comprising: providing a p-type semiconductor substrate; forming an-well region into said p-type semiconductor substrate; forming ashallow trench isolation (STI) into said p-type semiconductor substrateand a portion of said n-well region, thereby forming a PMOSFET activeregion and a NMOSFET active region; forming a channel into said PMOSFETactive region and said NMOSFET active region; forming a gate oxide layeron said PMOSFET active region and said NMOSFET active region; depositinga polysilicon gate on said gate oxide layer; etching said polysilicongate and said gate oxide layer, to form a PMOSFET gate pattern on saidPMOSFET active region and a NMOSFET gate pattern on said NMOSFET activeregion; forming a first defined photoresist layer over said PMOSFETactive region and a portion of said shallow trench isolation; implantinga n⁻-type dopant into said NMOSFET active region to form a n⁻-typelightly doped source/drain; removing said first defined photoresistlayer; depositing a first dielectric layer on said shallow trenchisolation, said NMOSFET gate pattern, said PMOSFET gate pattern, saidNMOSFET active region, and said PMOSFET active region; forming a seconddefined photoresist layer over said first dielectric layer; firstlyetching a portion of said first dielectric layer on said PMOSFET activeregion and a portion of said shallow trench isolation; forming an offsetspacer on said PMOSFET active region during a portion of said firstdielectric layer etching step; removing said second defined photoresistlayer; depositing a Si—B (silicon-boron) layer on a portion of saidshallow trench isolation, said PMOSFET active region, said PMOSFET gatepattern, said offset spacer, and said first dielectric layer; oxidizingsaid Si—B layer to form a BSG layer, thereby firstly diffusing boronatoms into said PMOSFET active region to form a p⁻-type lightly dopedsource/drain; depositing a second dielectric layer on said BSG layer;etching a portion of said second dielectric layer, a portion of said BSGlayer and secondly etching a portion of said first dielectric layer toform a first BSG spacer and a second BSG spacer; implanting a p⁺-typedopant into said PMOSFET active region to form a p⁺-type heavily dopedsource/drain; implanting a n⁺-type dopant into said NMOSFET activeregion to form a n⁺-type heavily doped source/drain; and annealing saidfirst BSG spacer, thereby secondly diffusing said boron atoms into abelow region of said first BSG spacer to form a source/drain extensionjunction in a PMOSFET.
 32. The method according to claim 31, whereinsaid p-type semiconductor substrate comprises a concentration less thanabout 1.0 E 15 atoms/cm.sup.3.
 33. The method according to claim 31,wherein said n-well region is formed, comprising ion implantationprocedures and phosphorus (P) as an ion source, at a energy betweenabout 100 KeV to 200 KeV, to implant a dosage between about 1.0 E 12 to1.0 E 13 atoms/cm.sup.2, then using a driving-in process, at atemperature about 1000.degree.C., to form a concentration about 1.0 E 16atoms/cm.sup.3.
 34. The method according to claim 31, wherein saidchannel is formed, comprising ion implantation procedures and boron (B)as an ion source, at a energy about 10 KeV, to implant a dosage about1.0 E 12 atoms/cm.sup.2.
 35. The method according to claim 31, whereinsaid channel is formed, comprising ion implantation procedures and boronfluoride (BF₂) as an ion source, at a energy about 10 KeV, to implant adosage about 1.0 E 12 atoms/cm.sup.2.
 36. The method according to claim31, wherein said gate oxide layer is formed, comprising a thermaloxidation.
 37. The method according to claim 36, wherein said thermaloxidation comprises a dry oxidation and a wet oxidation.
 38. The methodaccording to claim 31, wherein said polysilicon gate is formed,comprising low pressure chemical vapor deposition (LPCVD) procedures andsilane (SiH₄) as a source gas, at a temperature between about600.degree. to 650.degree.C., to a thickness between about 1000 to 2500angstroms.
 39. The method according to claim 31, wherein said n⁻-typelightly doped source/drain is formed, comprising ion implantationprocedures and phosphorus (P) as an ion source, at a energy less thanabout 30 KeV, to implant a dosage between about 1.0 E 14 to 5.0 E 15atoms/cm.sup.2.
 40. The method according to claim 31, wherein saidn⁻-type lightly doped source/drain is formed, comprising ionimplantation procedures and arsenic (As) as an ion source, at a energyless than about 30 KeV, to implant a dosage between about 1.0 E 14 to5.0 E 15 atoms/cm.sup.2.
 41. The method according to claim 31, whereinsaid first dielectric layer comprises silicon oxide, using LPCVDprocedures and TEOS as a source gas, at a temperature between about500.degree. to 800.degree.C., to a thickness between about 50 to 300angstroms.
 42. The method according to claim 31, wherein said firstdielectric layer comprises silicon nitride, using low pressure chemicalvapor deposition (LPCVD) procedures, at a temperature about750.degree.C., to a thickness between about 50 to 300 angstroms.
 43. Themethod according to claim 31, wherein said first dielectric layercomprises silicon oxide/silicon nitride, using low pressure chemicalvapor deposition (LPCVD) procedures, at a temperature between about500.degree. to 800.degree.C., to a thickness between about 100 to 300angstroms.
 44. The method according to claim 31, wherein said firstdielectric layer is firstly etched, comprising reactive ion etching(RIE) procedures with CHF.sub.3 as an etchant.
 45. The method accordingto claim 31, wherein said Si—B (silicon-boron) layer is deposited,comprising ultra-high vacuum chemical vapor deposition (UHV/CVD)procedures and a source gas, such as SiH₄ and B₂H₆, a thickness betweenabout 100 to 300 angstroms.
 46. The method according to claim 31,wherein said Si—B layer is oxidized to form said BSG layer, comprising arapid thermal processing (RTP), at a temperature between about950.degree. to 1000.degree.C., at a time between about 10 to 60 seconds.47. The method according to claim 31, wherein said boron atoms comprisesa concentration about 5.0 E 21 atoms/cm.sup.3.
 48. The method accordingto claim 31, wherein said second dielectric layer comprises siliconoxide, using low pressure chemical vapor deposition (LPCVD) proceduresand TEOS as a source gas, at a temperature between about 500.degree. to800.degree.C., to a thickness between about 500 to 2000 angstroms. 49.The method according to claim 31, wherein said second dielectric layercomprises silicon nitride, using low pressure chemical vapor deposition(LPCVD) procedures, at a temperature about 750.degree.C., to a thicknessbetween about 500 to 2000 angstroms.
 50. The method according to claim31, wherein said second dielectric layer is etched, comprising reactiveion etching (RIE) procedures with CHF.sub.3 as an etchant.
 51. Themethod according to claim 31, wherein said BSG layer is etched,comprising reactive ion etching (RIE) procedures with CHF.sub.3 as anetchant.
 52. The method according to claim 31, wherein said firstdielectric layer is secondly etched, comprising reactive ion etching(RIE) procedures with CHF.sub.3 as an etchant.
 53. The method accordingto claim 31, wherein said p⁺-type heavily doped source/drain is formed,comprising ion implantation procedures and boron (B) as an ion source,at a energy between about 1 KeV to 80 KeV, to implant a dosage betweenabout 1.0 E 15 to 1.0 E 16 atoms/ cm. sup.2.
 54. The method according toclaim 31, wherein said p⁺-type heavily doped source/drain is formed,comprising ion implantation procedures and boron fluoride (BF₂) as anion source, at a energy between about 1 KeV to 80 KeV, to implant adosage between about 1.0 E 15 to 1.0 E 16 atoms/cm.sup.2.
 55. The methodaccording to claim 31, wherein said n⁺-type heavily doped source/drainis formed, comprising ion implantation procedures and phosphorus (P) asan ion source, at a energy between about 10 KeV to 80 KeV, to implant adosage between about 1.0 E 15 to 1.0 E 16 atoms/cm.sup.2.
 56. The methodaccording to claim 31, wherein said n⁺-type heavily doped source/drainis formed, comprising ion implantation procedures and arsenic (As) as anion source, at a energy between about 10 KeV to 80 KeV, to implant adosage between about 1.0 E 15 to 1.0 E 16 atoms/cm.sup.2.
 57. The methodaccording to claim 31, wherein said boron atoms are secondly diffused,comprising a rapid thermal processing (RTP), at a temperature betweenabout 950.degree. to 1050.degree.C., at a time between about 10 to 60seconds.